This invention relates generally to a method of forming substrate vias for connecting a top surface via contact in an integrated circuit to a bottom surface ground plane and, more particularly, to a manufacturable method of forming the substrate vias in a thinned GaAs wafer.
Monolithic microwave integrated circuit ("MMIC") manufacturers are well aware of the need for low inductance source grounding to achieve high RF gain. Traditionally, source grounding was achieved by etching vias through the substrate and subsequently metallizing the vias with gold, providing a conducting path between the ground plane on the back of the die to front side interconnect of the die. The conductive paths through the semi-insulating GaAs substrate are known to improve the RF gain of MMIC amplifiers and therefore play a critical role in the circuit's electrical performance.
Until recently, the process for fabricating substrate vias in GaAs wafers has been accomplished with wet chemical etching or dry plasma etching. However, both of these techniques have undesirable characteristics. Dry chemical etching imposes increased safety risks, and wet chemical etching does not produce the uniform results needed for dependable, high yielding circuits. In addition, production throughput is limited by the etching rates using either of these techniques.
Production throughput can also be limited by the physical handling of the GaAs wafer. The top surface of the wafer must be protected during bottom surface processing. Typically, this is accomplished by coating the top surface of the wafer with a protective coating, or creating a sandwich of the GaAs wafer with a carrier wafer. As wafer sizes have increased to a four inch diameter, removing the protective coating or carrier wafer can be a difficult and slow process with attendant risks of damaging the wafer, thus limiting production throughput.
Accordingly, a need remains for a manufacturable method of fabricating vias in GaAs wafers that does not impose a safety risk, produces uniform results, has a well controlled depth, and does not limit production throughput or damage the wafer.